FIELD OF THE INVENTION
The invention lies in the semiconductor technology field. More specifically, the present invention relates to an integrated semiconductor memory having redundant units of memory cells for replacing normal units of memory cells, and to a method for self-repair of the semiconductor memory.
Integrated semiconductor memories, such as those described in German published patent application DE 198 19 254, generally have redundant word lines or redundant bit lines for repairing faulty memory cells. Those word lines or bit lines can replace the addresses of regular lines with defective memory cells. In that case, the integrated memory is tested, for example, using an external test facility or a self-test device, and the redundant elements are then programmed. A redundant circuit then has programmable elements, for example in the form of laser fuses or electrically programmable fuses, which are used to store the address of a line to be replaced. These are programmed, for example, in the course of the production process of the memory by means of a laser beam or a so-called burning or fusing voltage.
A functional test of a semiconductor memory with subsequent repair is normally carried out in a number of steps: in a first test configuration, functional tests are carried out on a semiconductor module which has been removed from its casing (wafer level test), and any defects found are repaired by programming the laser fuses. These tests are normally carried out in complex test systems with a high degree of parallelity for a number of semiconductor modules, in order to keep the test time and test expenses low. In a further test configuration, functional tests are carried out on the semiconductor module in its casing (module test). In contrast to defects which are found in a wafer level test, defects identified there are not repaired by means of laser fuses. The semiconductor module in its housing can be repaired in the appropriate test arrangement by programming electrical fuses, since these can also be programmed after the semiconductor module has been fitted into a casing, via electrical contacts.
One of the tests which until now have been carried out at wafer level is a so-called retention test. There, memory cells in a semiconductor memory are tested for the memory-retention time of the memory cell contents. Particularly in the case of dynamic semiconductor memories and in operating periods during which no access is being made to the memory cells, a so-called self-refresh mode is required in order to refresh the memory cell contents, which may be volatile (for example due to leakage currents), and thus to maintain them in the long term. The maximum achievable memory-retention time for the memory cell contents of a memory cell is the governing factor when determining the time period which is required between two self-refresh cycles. In the interest of a current drawer which is as low as possible, one aim is in this case to keep the time period between two self-refresh cycles as long as possible.
When carrying out a retention test, the memory-retention time is normally increased in discrete steps, for example from 256 ms to 384 ms and 512 ms. Depending on the test result, the tested semiconductor memories are sorted into different quality groups. The number of memory cells to be replaced is in practice highly dependent on the tested memory-retention time, with the number of faulty memory cells normally rising exponentially with the memory-retention time. The aim of a semiconductor memory module having a memory-retention time which is as long as possible contrasts with having a limited number of redundant units of memory cells. This means that the number of faulty memory modules rises if the required memory-retention time is long.
Since a large number of memory modules are tested in parallel, the testing time is relatively long in comparison with the number of fault-free memory modules. Thus, for example as a test phase progresses, a retention test with an increased memory-retention time is carried out for all the memory modules to be tested in parallel although, even at this stage, some of the memory modules do not satisfy the requirements of a previous retention test. The tests are normally carried out up to a defined memory-retention time, in order to prevent the test time from becoming excessively long. This leads to the outcome that certain memory modules, whose quality with regard to the memory-retention time is potentially higher, are not identified.
In the above-mentioned German document DE 198 19 254 A1, it is proposed that a faulty chip identification circuit unit be provided in order to reduce the overall testing time of a chip having a DRAM unit and a logic unit, by means of which faulty chip identification circuit unit a tester of the logic unit can identify, in particular, whether the DRAM unit is faulty, so that it is possible to save a complex and useless investigation of the logic units of chips with faulty DRAM units. To this end, at the time when the DRAM unit is tested, which takes place before the logic unit is tested, when the decision is made that the DRAM unit cannot be made to conform even by using a redundant circuit, the fault data are written to the faulty chip identification circuit unit. These data are then identified by the tester of the logic unit.